Generally, a memory device comprises a memory cell array, a selecting circuit and a sense amplifier. The selecting circuit is electrically connected to the read bit lines arranged in the memory cell array, and the selecting circuit is configured for selecting one of the read bit lines and referring the signal on the selected read bit line as an output signal. The sense amplifier is configured for comparing the voltage level of the output signal of the selecting circuit with a reference voltage having a constant voltage level and outputting a sensing result accordingly. Therefore, an electronic apparatus adopting the memory device can interpret the content stored in a selected memory cell to be either logic “1” or logic “0” according to the sensing result.
However, an electrical leakage always occurs on each of the read bit lines so the voltages on the read bit lines do not completely correspond to the content stored in the selected memory cell. In other words, the sense amplifier will compare an inaccurate voltage level with the voltage level of the reference voltage, causing an incorrect sensing result. As a result, the electronic apparatus adopting the memory device will not correctly interpret the content of the selected memory cell according to the sensing result outputted from the sense amplifier.